H5TQ2G63GFR-RDC

H5TQ2G63GFR-RDC is a 128M FBGA96 DDR3 Memory chip on the Whatsminer CB2-V8 control board, which is very suitable for main memory applications that require large storage density and high bandwidth. It provides fully synchronous operation on the rising and falling edges of the reference clock. The data path uses an internal pipeline and 8-bit prefetch to achieve high bandwidth.

Feature:

• Fully differential clock input (CK, CK) operation

• Differential Data Strobe (DQS, DQS)

• On-chip DLL aligns DQ, DQS, and DQS transitions with CK transitions

• DM mask writes data on the rising and falling edges of the data strobe

• All address and control inputs except data, data strobe, and data mask that are latched on the rising clock edge

• Programmable burst length 4/8 with nibble order and interleaved modes

• Average refresh cycle (Tcase 0 ℃ ~ 95 ℃)

- 7.8 µs from 0°C to 85°C

- 3.9 µs from 85°C to 95°C

Commercial temperature (0℃ ~ 95℃)

Industrial temperature (-40℃ ~ 95℃)

• JEDEC standard 96-ball FBGA(x16)

• Driver strength selected by EMRS

• Supports dynamic on-chip termination

• Supports asynchronous RESET pin

• Support ZQ calibration

• TDQS (Terminate Data Strobe) support (x8 only)

• Support write leveling